1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an NPN Darlington ESD protection circuit.
2. Description of the Prior Art
Static electricity is everywhere, because it is very possible to form static electricity by rubbing together any two bodies of different materials. When a body having static electricity touches metal pins of an IC, it will discharge high voltage to damage the internal circuit through the metal pins of the IC. Electrostatic discharge (ESD) will cause the electrical system to lose efficacy. When electrostatic discharge occurs, an electrostatic discharge protection circuit can act before a pulse of electrostatic discharge arrives at the internal circuit to eliminate the high voltage immediately and decrease the damage by the electrostatic discharge. Simultaneously, the protection circuit also has to sustain the energy of the electrostatic discharge and not damage itself. Additionally, the protection circuit acts only when electrostatic discharge occurs to prevent electrostatic discharge from influencing normal operations.
Please refer to FIG. 1. FIG. 1 is a schematic view of a BJT ESD protection circuit according to the prior art. As shown in FIG. 1, in a BiCMOS application, an NPN BJT is used as an ESD protection circuit. A base of the NPN BJT is floating, an emitter is grounded, and a collector is connected to an input pad or a VDD pad of an internal circuit. When the input pad or the VDD pad of the internal circuit is influenced by an electrostatic discharge, the NPN BJT operates in breakdown to ground current of the electrostatic discharge. The advantage of using the open-base NPN BJT as an ESD protection circuit is the small input capacitance of the NPN BJT. However, the NPN BJT has a current limitation such that the protection effect is poor, this being the shortcoming of using the open-base NPN BJT as the protection circuit.
Please refer to FIG. 2. FIG. 2 is a schematic view of a MOS ESD protection circuit according to the prior art. As shown in FIG. 2, a MOS is used as an ESD protection circuit. A gate of the MOS is connected to a source, the source is grounded, and a drain is connected to an input pad or a source pad of an internal circuit. When the input pad or the source pad of the internal circuit is influenced by an electrostatic discharge, the MOS turns on to ground current of the electrostatic discharge. The advantage of using a gate-grounded MOS as an ESD protection circuit is better ESD protection because the MOS is capable of handling a large current. However, the shortcoming of using gate-grounded MOS as an ESD protection circuit is that the MOS has a larger input capacitance, so the operation speed of the MOS is too slow in providing complete protection to the internal circuit.
According to the above-mentioned ESD protection circuits, using an open-base NPN BJT as an ESD protection circuit has a fast operation speed but a poor ESD protection effect, and using gate-grounded MOS as an ESD protection circuit has a better ESD protection effect but an operation speed that is limited because of the larger input capacitance.
For other related techniques please refer to U.S. Pat. Nos. 5,530,612, 5,986,863, 6,028,758, 6,320,735, and 6,400,540, U.S. filing Pat. No. 20020027755A1, and European Patent Numbers 651,490 and 477,429.